1. Technical Field
The present invention relates in general to data processing and, in particular, to functional verification of a processor. Still more particularly, the present invention relates to a processor and method of testing a processor for hardware faults through execution of a pipeline interlocking instruction.
2. Description of the Related Art
A typical superscalar microprocessor is a highly complex digital integrated circuit including, for example, one or more levels of cache memory for storing instructions and data, a number of execution units for executing instructions, instruction sequencing logic for retrieving instructions from memory and routing the instructions to the various execution units, and registers for storing operands and result data. Interspersed within and between these components are varies queues, buffers and latches for temporarily buffering instructions, data and control information.
As will be appreciated, at any one time the typical processor described above contains an enormous amount of state information, which can be defined as the aggregate of the instructions, data and control information present within the processor. Because of the size of the processor's state space, it is difficult to adequately test for combinations of internal conditions (e.g., full queues or buffers, certain instruction sequences, etc.) that can produce hardware functional errors by simulation testing or post-fabrication hardware testing utilizing conventional instruction streams. Such conventional methods of functional verification simply do not reliably induce or model “corner cases” (i.e., infrequently occurring combinations of internal states) that are likely to result in functional errors.
Thus, while complex circuitry such as processors can be tested for manufacturing faults, for example, utilizing conventional IEEE 1149.1 boundary scan testing, no method of performing full functional verification on a complex superscalar processor is currently available. Consequently, many conventional processors remain only partially tested, thus permitting hardware functional errors to remain undetected until after fabrication or release.